ASIC Physical Design Engineer - Low-Latency Hardware
Job Description
[Up to c. $475k Comp Package | Hybrid Working]
Role Overview
We’re representing a leading quantitative trading firm building highly specialised hardware systems for performance-critical trading and research workloads. The hardware group develops custom compute platforms across FPGA and ASIC technologies, with a focus on reducing latency, increasing throughput and enabling highly differentiated trading infrastructure.
This role is focused on physical design for advanced ASIC programmes. You’ll work across implementation, timing closure, design methodology, automation and signoff, helping deliver high-performance chips on modern process nodes. The ideal profile is not a narrow execution-only physical design engineer; they want someone with breadth across the end-to-end physical design ecosystem who can improve methodology, diagnose complex issues and work closely with RTL, architecture and broader hardware teams...
Key Responsibilities
- Drive physical implementation work across advanced ASIC designs, from RTL handoff through final signoff
- Contribute to floorplanning, placement, routing and optimisation for performance-sensitive hardware
- Own timing closure activity across complex mode and corner scenarios
- Analyse and resolve implementation challenges including congestion, timing failures, IR drop and EM concerns
- Improve physical design methodology, automation and repeatability across the design flow
- Build scripts and internal tools to parse design data, surface issues and increase engineering productivity
- Work closely with RTL, architecture and hardware engineers to influence design decisions earlier in the lifecycle
- Support DFT implementation and testing approaches as part of the wider ASIC delivery process
- Use data-led analysis to improve power, performance, area and design robustness
- Help evolve physical design practices for future high-performance ASIC and accelerator programmes
What You’ll Bring…
- 5-12 years’ experience in ASIC physical design, implementation or signoff within high-performance chip environments
- Strong understanding of digital design, circuit fundamentals and modern semiconductor process considerations
- Hands-on experience across physical implementation flows, ideally on advanced technology nodes
- Strong static timing analysis experience, including timing closure across multi-mode, multi-corner designs
- Experience with industry-standard EDA tooling such as Innovus, PrimeTime or comparable physical design / signoff platforms
- Experience analysing timing, power or implementation data using statistical or data-driven methods
- Strong scripting and automation ability using Python, Tcl, shell or similar
- Ability to diagnose difficult physical design failures and improve underlying methodology rather than only execute flows
- Understanding of DFT concepts and how test requirements influence physical implementation
- Ability to work across the full ASIC design lifecycle, collaborating effectively with architecture, RTL and verification teams
- (Preferred) Background in AI accelerators, networking silicon, trading hardware, high-performance compute, automotive compute or similar performance-critical ASIC environments
- (Preferred) Experience in smaller or highly collaborative teams where engineers own broader portions of the design flow rather than narrow execution tasks
...
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